In the fabrication of integrated circuits, various conductive layers are used. For example, during the formation of semiconductor devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), ferroelectric (FE) memories, etc., conductive materials are used in the formation of storage cell capacitors and also may be used in interconnection structures, e.g., conductive layers of contact holes, vias, etc.
As memory devices become more dense, it is necessary to decrease the size of circuit components forming such devices. One way to retain storage capacity of storage cell capacitors of the memory devices and at the same time decrease the memory device size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. Therefore, high dielectric constant materials are used in such applications interposed between two electrodes. One or more layers of various conductive materials may be used as the electrode material.
Generally, various metals and metallic compounds, for example, metals such as ruthenium and platinum, have been proposed as the electrodes for at least one of the layers of an electrode stack for use with high dielectric constant materials. Many storage cell capacitors are fabricated which include electrode layers that are formed of a conductive material within a small high aspect ratio opening. One particularly preferred material for forming an electrode in a high dielectric capacitor is platinum. However, one of the problems typically associated with the use of platinum is the lack of a practical etch process. Thus, conventional techniques used to form a platinum electrode include CMP (chemical-mechanical polishing) or ion milling. However, these techniques pose particular problems when utilized for forming patterned platinum features. For example, CMP is typically used to achieve a planar surface over the entire wafer and/or chip. However, it may be difficult to polish a layer formed within a small high aspect ratio opening using CMP. Ion milling typically includes the use of a broad ion beam to impinge on the wafer surface in a defined direction with respect to the feature to be etched. However, due to the physical characteristics of platinum, ion milling is generally difficult to perform, for example, it is typically a relatively slow and non-selective process which may result in an over etching of underlying layers.